PERSONAL PROJECT · 2024
RISC-V 32I Base Integer Microprocessor
A from-scratch RV32I processor in Verilog, with single-cycle and 5-stage pipelined implementations, hazard handling, and M-extension support.
A from-scratch implementation of the RISC-V RV32I base integer instruction set in Verilog, built to explore processor microarchitecture beyond the textbook: a single-cycle datapath alongside a modular 5-stage pipeline (fetch, decode, execute, memory, write-back).
The pipelined version handles data and control hazards directly — forwarding and stalling logic live in a dedicated hazard unit rather than being bolted onto the datapath — and the instruction set was extended with the M (multiply/divide) extension on top of the RV32I base.
Every module — ALU, control unit, register file, hazard unit — is verified independently with its own testbench before integration, and the full core is validated against the RISC-V specification through simulation.
Highlights
- Implemented the RV32I base integer ISA with both a single-cycle datapath and a 5-stage pipelined microarchitecture (IF/ID/EX/MEM/WB).
- Designed a dedicated hazard unit for data and control hazard detection, with forwarding and stalling to keep the pipeline correct under dependencies.
- Extended the ISA with the M (multiply/divide) extension on top of the RV32I base.
- Verified each module independently via testbenches, then validated the integrated core against the RISC-V specification through simulation.